MOSFET Short Circuit Failure — Root Cause & 8D

What Is a MOSFET Short-Circuit Failure?

A short-circuit failure is the most common destructive failure mode of power MOSFETs. The drain-source channel becomes a near-zero resistance path, the gate oxide usually ruptures as well, and the device is destroyed — often explosively. In motor drives, DC-DC converters and inverters the root cause is frequently not the MOSFET itself but the circuit around it: parasitic inductance, gate drive design, or a design review that did not include a power-electronics specialist. This makes it a textbook D4 investigation where the evidence lives in the switching waveform.

Symptoms

• Drain-source resistance near zero (a dead short)
• Gate-source also short (usually below 100 Ω) from gate oxide rupture
• Crater or burn mark on the package; localised PCB discolouration
• Fuse blown or over-current protection tripped
• Failure immediately at power-up, or after a period of running under load
• Avalanche or thermal-runaway signature in the failure analysis

Affected Components

• Power MOSFETs (Si, SiC, GaN) in motor drives, DC-DC converters and inverters
• Gate driver ICs and gate resistors
• PCB switching loops (the high dV/dt and dI/dt commutation path)
• Snubber circuits, TVS diodes and gate-source zener clamps

Detection Methods

• Curve tracer / semiconductor analyser: measure Vgs(th), Rds(on) and BVdss against the datasheet
• X-ray / CSAM: die attach voiding and wire bond lift-off
• Decap and microscopy: visual inspection of the die for ESD damage, hot spots and gate oxide rupture
• Emission microscopy / liquid crystal: locate the hot spot before physical failure analysis
• Double-pulse test: measure Vds overshoot, gate ringing and dV/dt under real switching conditions

Possible Causes

• Drain-source overvoltage (avalanche): turn-off ringing across parasitic inductance drives Vds above BVdss and exceeds the single-pulse avalanche energy (Eas).
• Gate overvoltage: Miller effect and gate loop inductance push Vgs beyond the ±20 V rating.
• ESD: HBM or CDM events during handling exceed the rated ESD level.
• Thermal runaway: Rds(on) rises with temperature, which increases I2R heating, which raises Rds(on) further until the die fails.
• Shoot-through: insufficient dead time makes the high-side and low-side devices conduct simultaneously.
• dI/dt induced turn-on: fast switching couples through the Miller capacitance and parasitically turns the device on.

5-Why Example

Problem: Low-side MOSFET shorted during regenerative braking in a three-phase inverter.

1. Why did the MOSFET short? → Vds avalanche breakdown
2. Why was there overvoltage? → Ringing reached 135 V on a 100 V MOSFET
3. Why was the ringing so severe? → About 25 nH of parasitic inductance in the DC-link layout
4. Why was the inductance not controlled? → The PCB layout was reviewed by a digital engineer, not a power electronics engineer
5. Why was the reviewer wrong? → The design review checklist did not require power electronics layout review

TRC: Parasitic inductance ringing caused MOSFET overvoltage failure. MRC: The design review process did not ensure a power electronics specialist reviewed the high-current PCB layout.

Fishbone (6M)

• Man: Layout engineer not familiar with high dI/dt loop optimisation
• Machine: DC-link capacitor 40 mm from the MOSFET, creating a large commutation loop
• Method: Gate resistor of 2.2 Ω is too low and causes gate ringing; no snubber on the switching node
• Material: Eas of 50 mJ is marginal for the operating condition
• Measurement: Switching waveforms checked only at 25 °C, where behaviour is best
• Environment: Regenerative braking raises the DC-link from 48 V nominal to 85 V

D3 Containment

• Limit the DC-link to 75 V during regenerative braking via a firmware change
• Increase the gate resistor from 2.2 Ω to 10 Ω to damp ringing
• Add a drain-source TVS clamp to all products
• 100% switching waveform check at 85 °C on critical batches

D5 Permanent Fix

• Redesign the PCB so the DC-link capacitor sits within 10 mm of the MOSFET, using a laminated bus bar
• Add an RCD snubber to each half bridge
• Select a 150 V BVdss MOSFET with Eas above 200 mJ
• Add active gate-source clamping (zener plus BJT)

D7 Prevention

• Mandatory power electronics layout sign-off in design review
• Mandatory 125 °C junction double-pulse testing for all new designs
• Update the DFMEA to raise the occurrence and detection scores for parasitic inductance

Key Takeaways

1. The MOSFET is usually the victim, not the culprit — investigate the switching loop first.
2. Parasitic inductance and gate ringing are the two dominant causes in real designs.
3. Double-pulse testing at high temperature reproduces failures that room-temperature tests miss.
4. A design review without a power electronics specialist is a systemic risk.
5. Containment must limit voltage and current immediately, then fix the layout.